Optimization of phase change RAM write performance for large memory array

This paper analyzes the crystallization statistics and optimizes the performance of complex doped GST on 256 kb memory arrays in 180 nm CMOS technology. A novel method of deriving an optimized SET strategy from the RESET current distribution is developed. This significantly improves performance and results in 200 ns SET time. A large Rreset/Rset ratio can be maintained even after 8E6 cycles.