A performance evaluation methodology for computer systems

This paper presents a simulation methodology for evaluating the performance of CISC and RISC computer systems. Our method is called message flow technique (MFT). MFT is a modification of the instruction flow technique (IFT) we presented for RISC previously. The proposed methodology was applied to a single and two-level cache-based complex instruction set computer system using 80486 SX as a case study. Our trace driven simulations provide an estimate of the mean performance of the system for the considered general purpose computing environment with an accuracy of /spl plusmn/5% and a confidence level of 95%. The simulations indicate that with a single level on-chip cache of size 8 K bytes, the performance of the system is considerably limited by the service rime of bus interface unit (BIU). The average service time of bus interface unit, per instruction, was found approximately equal to 1.0135 microseconds for our synthetic workloads, collectively called, modified Gibson mix (MGM). With the introduction of a moderate-sized second level external cache to the system, the average performance improvement was found to be appreciable. The methodology presented here is an efficient and easy to use tool as compared to the previous methodologies, essentially limited to RISC architectures, that could help performance analysts in evaluating different computer systems.<
>