A Radix-8 Log-MAP recursion VLSI architecture

This paper presents a high speed Radix-8 Log-MAP turbo decoder recursion architecture: algorithmic approximation and architectural optimization are incorporated in the proposed designs to reduce the critical path. The synthesis results show that the proposed design has a high throughput of 693 Mbps in 0.18 um CMOS technology, which is nearly 3 times higher than using conventional Radix-2 architecture. The hardware complexity is only linearly increased with the new design. The simulation with AWGN channel shows that the proposed design has generally less than 0.05 dB performance degradation from the true Log-MAP decoder.