Automatic test plan generation for analog and mixed signal integrated circuits using partial activation and high level simulation

This paper introduces a novel technique to generate test plans automatically for analog and mixed signal integrated circuits (ICs), which are designed using modular design concept similar to that of digital integrated circuits. In such structured, top-down, modular design methodology of analog and mixed signal integrated circuits, each block in the design is represented by a high level but accurate model, which describes its behavior across the inputs and outputs (IOs) of the block. These high level models of the blocks are created during the design of the complete chip, and are used for the simulation of the complete device. Given the design database of a chip, designed using these blocks, the proposed algorithm generates test plan for all the blocks of the chip. First the test values are set on the block to be tested, which may or may not be directly accessible from the design IOs of the IC. The algorithm tries to find a consistent set of values to be set at the design IOs, preserving the test values set on the internal block under test. Test plan generated consists, the values to be set and measured at the design IOs of the IC, for carrying out the tests on that block. Unlike the previous propagation based method, this method uses high level simulation. "Partial Activation" and "Distance Heuristics" concepts are introduced. Several disadvantages of the previous method are eliminated. Comparative results are found to be remarkably better than the previous method. Implementation of this algorithm is presented with examples and results.<
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