Post-layout optimization of power and timing for ECL LSIs

An optimization algorithm for power and timing of bipolar ECL LSls is proposed. The power dissipation is minimized by a nonlinear programming solver under accurate timing constraints extracted from layout. The power and delay time of an ECL gate are considered functions of its switching current which is regulated by programming its resistors. Experimental results show significant power reductions for circuits including a real chip without degrading the performance.<
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