The effect of pin constraints on layout area

We present an improved area estimation model that considers the large influence of pin positions on the layout area. The estimation method is based on the shape function approach described by Zimmermann (1988). A cell is abstracted at all hierarchy levels by discrete shape functions describing its area with respect to its shape. The internal wiring area is estimated by a simple but proper statistical model. Although the basic approach is one of the most accurate hierarchical area estimation models, it is based on internal wiring only. Additional area that is needed for the wiring to the cell border is estimated very roughly. However, in many cares, especially during top-down design, the layout area depends very much on the pin positions. In this paper, we present an improved model that estimates the influence of pin positions on the layout area much better.<
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