A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery

This paper describes a 1.5 Gb/s and 3 Gb/s serial PHY architecture aimed at robust operation and ease of porting to smaller technologies. A minimum of precision analogue functions are used, and all digital functions use rail-to-rail CMOS. A single fixed low-jitter PLL serves the transmit and receive paths in both modes, and a new oversampling CDR relaxes the requirements for the analogue front-end as well as for the signal quality. The design occupies <0.4 mm
²
in 90 nm CMOS and consumes 75 mW.