FPGA Design and Implementation of an Improved 32-bit Binary Logarithm Converter

This paper presents an improved 32-bit binary logarithm converter, which is optimized according to the characteristics of Xilinx Virtex4 series FPGA. The implementation in FPGA denotes that our improved method not only costs less resources but also has much higher speed. Meanwhile a novel and simple error correction method is proposed. It reduces the converter error to only one half of the Metchell's method. The analytical results of the approximation error are confirmed by numerical simulation results.