Measurement techniques for on-chip power supply noise waveforms based on fluctuated sampling delays in inverter chain circuits

To evaluate an on-chip power supply noise waveforms for power integrity design, we have developed a technique for measuring on-chip voltage waveforms. To overcome trade-offs in voltage resolution and the measurable frequency band, we designed inverter chain circuits that change the lengths of series inverters: a short chain provides low frequency and high resolution, while a long chain provides high frequency and low resolution. We measured on-chip noise waveforms using a 90 nm CMOS test chip with a 50 -inverter chain circuit as small as 320 square micrometers, confirming that the circuit could achieve a voltage resolution of 1 mV and temporal resolution of 20 ps. The amplitude of the noise waveform generated by the noise source circuits is proportional to the activating ratio of the source, although resonance frequencies are virtually the same - 160 MHz - when the activating ratios change.