A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation

A spread spectrum clock generator is implemented in a 0.18μm CMOS process employing the proposed piecewise linear modulation profile to significantly reduce EMI with a simple implementation. A high resolution fractional divider to reduce quantization noise from the modulation is proposed as well. A peak power reduction level of 14.2dB with 5000ppm down spreading and 27.88ps
pp
of jitter in the SSCG without modulation are measured.