A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling

A 1.2V 12b 30MS/s pipelined ADC, implemented in a 65nm standard CMOS technology, achieves an SNDR of 65.1dB with a rail-to-rail 4.7MHz input. A capacitive reference scaling technique is proposed to alleviate the high gain requirement of the opamp and a wide input range of 2.4Vp-p differential for low voltage operation in the nanometer domain. The prototype ADC dissipates 18mW and occupies an active die area of 0.34mm
²
. The measured DNL and INL are ± 0.44LSB and ±1.33LSB, respectively.