An FPGA-based digital class-D amplifier using short word-length

A digital Class-D amplifier based on single-bit processing to be implemented on a field programmable gate array (FPGA) is presented. The main focus of this design is the reduction of noise, a drawback of Class-D amplifiers, by exploring the noise-shaping characteristics of sigma-delta modulation (SDM). The audio signal is retained in the digital single-bit domain until the final stage of the amplifier, thus avoiding quantization noise due to conversion. This paper focuses on the SDM and digital signal processing (DSP) components of the design to be implemented on the FPGA.