Energy-optimal signaling and ordering of bits for area-constrained interconnects

Narrow-width and multiplexed buses are suitable for underutilized interconnects in microprocessors to reduce area/cost with minimal performance overheads. However, due to the interleaving of uncorrelated traffic, they have higher switching activity and energy dissipation compared to demultiplexed buses. We demonstrate the effectiveness of energy-optimal bit signaling and ordering for multi-plexed buses in significantly reducing this energy overhead across SPEC CPU2k benchmarks.