Theoretical analysis of power clock generator based on the switched capacitor regulator for adiabatic CMOS logic

This paper reports an analytical method of a power clock generator based on a switched capacitor circuit which is used in adiabatic logic. We derive first an equivalent circuit model of the switched capacitor circuit. We then discuss the design optimization of the capacitance ratio. Finally, we show that the analytical results agree rather well with the SPICE simulation results.