Lateral and Vertical Scaling of $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ HEMTs for Post-Si-CMOS Logic Applications

In this paper, we have experimentally investigated the impact of lateral and vertical scaling of $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ high-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing the $\hbox{In}_{0.52}\hbox{Al}_{0.48}\hbox{As}$ insulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length of around 60 nm. Our nearly enhancement-mode 60-nm HEMTs feature $V_{T} = -\hbox{0.02 V}$, $\hbox{DIBL} = \hbox{93 mV/V}$, $S = \hbox{88 mV/V}$, and $I_{\rm ON}/\break I_{\rm OFF} = \hbox{1.6} \times \hbox{10}^{4}$, at $V_{\rm DD} = \hbox{0.5 V}$ . We also estimate a gate delay of $CV/I = \hbox{1.6 ps}$ at $V_{\rm DD} = \hbox{0.5 V}$. We have benchmarked these devices against state-of-the-art Si CMOS. For the same leakage current, which includes the gate leakage current, the InGaAs HEMTs exhibit $\hbox{1.2}\times$ more current drive $(I_{\rm ON})$ than the state-of-the-art 65-nm low-power CMOS technology at $V_{\rm DD} = \hbox{0.5 V}$.