Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

Forward body biasing is a promising approach for realizing optimum threshold-voltage $(V_{\rm TH})$ scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias $(V_{F})$ decreases the depletion width $(X_{\rm DEP})$ in the channel region, it reduces $V_{\rm TH}$ rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small $X_{\rm DEP}$ ) at low $V_{\rm TH}$ notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for $\vert V_{F}\vert$ should be set at 0.6–0.7 V, which is sufficient to realize significant advantages of forward body biasing.