A reusable distributed arithmetic architecture for FIR filtering

This paper presents a new hardware efficient distributed arithmetic (DA) architecture for high order (≫ 1024) digital filters. The new architecture is termed reusable distributed arithmetic (RDA). The proposed architecture has a linear dependence of memory size on filter length versus the exponential dependence found in lookup table (LUT)-based designs by removing the LUT and generating the required combinations online. In addition, the proposed RDA architecture reuses the computation blocks much like the way multipliers are reused in multiplier-based architectures to reduce hardware complexity. The proposed RDA design is compared against a multiplier-based (MM) design to illustrate the area dependency of both designs on filter length. FPGA synthesis results confirm that the RDA design is capable of much higher order filters (2048 tap) than the MM design (512 tap) while at the same time having similar equivalent gate counts and throughput.