CMOS PA design dedicated to UMTS (3G) applications in 65 nm technology

This paper deals with the challenges of designing and implementing a PA dedicated to 3G applications in a CMOS 65 nm technology. High linearity and high power applications impose several bottlenecks from the layout point of view. The difficulties are increased by the use of a low cost technology. Reduce the size of the circuit while increasing the power leads to think of a different layout topology. The PAE (power added efficiency) in this type of application is generally low, making the thermal effect, even more critical. The layout will be used as an example to highlight the compromises that have been made along the process. Thanks to a new PA structure and a very carefully layout, this CMOS power amplifier provides a 31 dBm maximal output power with a PAE of 25% at 1.95 GHz.