A flexible sample and hold circuit for data converter applications

The sample and hold circuit is perhaps the most important building block in most data acquisition systems such as data converter. Flexibility of this block can be used to improve the whole performance of the system. In this work a flexible structure with variable gain is presented. The circuit is used to calibrate a typical time interleaved analog to digital converter. Simulation results indicated that modified circuit is superior in some aspects to the commonly used architectures. Designed circuit is simulated in a standard 0.35 um CMOS technology, the SHA achieves 87 dB SFDR for 2 Vpp input at 200 MHz sampling rate. The performance is not degraded for input’s frequency up to the Nyquist frequency.