Design of an ultra-low power time interleaved SAR converter

An ultra low-power SAR ADC is presented. The circuit is the interleaved version of an already designed SAR converter with improved performance. This design uses 7 interleaved converters and achieves a conversion rate of 700 kS/s. The converter has been simulated by using a 0.18-mum CMOS technology showing a power consumption as low as 40 muW which allows obtaining a state-of-the-art FoM equal to 37 fJ/conv.-step. The architectural study together with converter simulation results are presented.