A Scalable Digitalized Buffer for Gigabit I/O

A serial input-output (I/O) composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the simultaneous switching noise simultaneously. With a TSMC 0.18-mum CMOS process, the I/O occupies an area of 0.014 mm
²
and operates from 4 Gbps@1.9 V to 1.5 Gbps@1.1 V.