Two-bit cell operation in diode-switch phase change memory cells with 90nm technology

This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are 1) the write-and-verify (WAV) writing of four-level resistance states and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diode-switch phase change memory cells with 90nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 10
⁸
cycles, respectively. In addition, they are non-destructively readable above 10
⁷
read pulses at 100ns and 1uA.