Low-power Digital Filter Using Optimized CSD and Pipelined AU for 24-bit Audio DAC

A new optimization algorithm of the digital filter over the CSD coefficient is proposed. This method is based on the selective weighting method assigning more number of operations to some coefficients which are more sensitive to the frequency response remaining total number of operations. Also, the optimized coefficient is utilized as Control-RAM and combined with the 4
^th
pipelined AU for the low-power implementation. The designed filter for 24-bit Σ◻ audio DAC is fabricated with 0.18um Samsung CMOS technology.