A teraBit/s-throughput, SerDes-based interface for a third-generation 16 core 32 thread chip-multithreading SPARC processor

Third-generation 16 core 32 thread chip-multithreading SPARC processor interface has 1.1 Tbps I/O throughput with 112 Tx/176 Rx SerDes channels in 46 mm
²
. Individual links run at BER of 1E-12 on FR4 PCBs at 4.08-0.5 Gbps full-half rate, and 18 mW/ch/Gbps at 2.67 Gbps. Each link has linear equalization, 15 deemphasis and 8 output-swing control settings, and latency of 8UI in Rx and 14-16UI in Tx.