A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell

An asymmetric memory interface cell with 32 bidirectional data and four unidirectional request links operating at 16 Gb/s per link is implemented in TSMC 65 nm CMOS process technology. Timing adjustment and equalization circuits for both memory read and write are on the controller to reduce the memory cost. Each link operates at a maximum rate of 16 Gb/s with sufficient and comparable margins in both directions at a BER of 10
^-12
. The measured energy efficiency for the controller interface cell is 13 mW/Gb/s under nominal operating conditions.