Picosecond delay adjustment for 12.8 Gbps multiplexed testing

A novel high-bandwidth adjustable delay circuit is described that is used for XOR-based multiplexing of multi-Gbps test signals. By precisely-aligning the phase offset of two 6.4 Gbps ATE signals, an Indium-Phosphide exclusive-OR gate is used to synthesize a double-data-rate signal with picosecond resolution and ~30 ps accuracy. The delay circuit is based on an experimentally-observed second-order effect in a SiGe variable-amplitude differential buffer. A 2-channel module for testing serial and parallel signals up to 12.8 Gbps is described. The performance of the module is demonstrated between 6.4 Gbps and 12.8 Gbps.