High-speed highly-linear CMOS S/H circuit

This paper describes the high-speed and highly-linear CMOS sample/hold circuit that was used in front end of an ADC. The architecture of sample/hold based on an open-loop structure that enables it operates in high speed. The sample/hold consists of highly linear open-loop buffer and bootstrapped switch. Spice simulation with 0.35-um CMOS BSIM3v3 model parameters showed the SNDR (signal to noise-distortion ratio) more than 72 dB and 64 dB for 20 MHz and 50 MHz 1 Vp-p sinusoidal inputs respectively at 200 MS/s with 3.1 mW power consumption.