Fuzzy Logic Arbiter for Shared Bus Multiprocessor System: A Design Approach

On-chip communication architecture plays an important role in determining the overall performance of the System-on-Chip (SoC) design. In the recourse sharing mechanism of SoC, the communication architecture should be flexible to offer high performance over a wide range of traffic. The paper describes and evaluates the use of fuzzy logic arbiters for shared-bus multiprocessor system. In such systems, arbiters are used to resolve conflicts between processor requests shared bus. Typically, these conflicts are resolved by using two-stage arbitration schemes that employ policies such as random choice, daisy chaining, round-robin, etc. A new way of implementing these arbiters is the use of fuzzy logic to resolve resource request conflicts based on the system state and performance variables. This paper proposed a new technique for implementation of fuzzy logic in the system arbiters and presents a simulation program. The inputs are fuzzified by using appropriate membership functions, and rules have been defined in such a way as to increase and distribute evenly the acceptance rate of each processor in the system