Low-voltage limitations and challenges of nano-scale CMOS LSIs - A personal view of memory designer -

The minimum operating voltage (V
min
) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V
min
that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (V
T
) of MOSFETs. The V
min
, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce V
T
variations.