High Performance Architecture Design of CAVLC Encoder in H.264/AVC

Context-based adaptive variable length coding (CAVLC) is a new and important feature of the H.264/AVC. Based on analysis and modification of the conventional run-length coding architecture, a novel high efficiency VLSI architecture for H.264/AVC CAVLC encoding is presented in this paper. An approach called arithmetic table structure is exploited to replace look-up-table ROM for reducing hardware resource. Moreover, a modified VLC packer is used to increase the throughout of CAVLC encoder architecture. With the synthesis constrain of 133 MHz, the hardware cost of the proposed design is 13113 gates based on 0.18 CMOS technology. Simulations show that the proposed design is capable of real-time processing for 1920 1080 30fps videos.