A decimal-to-decimal antilogarithmic converter

This paper presents a novel design and implementation of a 7-digit fixed-point decimal-to-decimal antilogarithmic converter. A linear approximation algorithm is proposed and simulated in MATLAB models. The maximum absolute error of the proposed decimal antilogarithmic converter is in the range of -0.000999 les E
_absolute
les 0.000857 and the maximum percent error is in the range of -0.000715 les E
_percent
les 0.000691. The proposed decimal-to-decimal antilogarithmic converter is modeled in VHDL and implemented using a Xilinx Virtex-II Pro P30 FPGA device. The converter is implemented using combinational logic only and it computes decimal antilogarithms results in a single clock cycle, running at 53.1 MHz.