A Study of the Write Gate for Bloch Line Memory Devices

The write gate for Bloch line memory devices has been investigated by computer simulations and experiments. In the case of conventional gates where a write conductor is located at the stripe domain head, computer simulations showed that the VBL pair generation takes place in such a way that the horizontal wall magnetization between the generated VBLs is opposite in direction to the applied in-plane field H
ip
. As a result, the VBLs collapse easily when the write current is small. To correct this shortcoming, a new write gate, in which the write conductor is located along the stripe domain wall, has been designed and examined. In this gate, VBLs are stable because the generated VBLs have a horizontal magnetization in the same direction as H
ip
. While the current margin of a conventional gate is about 6%, the new gate has been confirmed experimentally to show a greatly improved current margin, as high as 77%, at an H
ip
of 7 Oe.