A 5GHz CMOS PLL with low KVCO and extended fine-tuning range

A 5 GHz dual-path integer-N PLL uses an LC VCO and softly switched capacitors in the integral path to extend the fine-tuning range while keeping K
_VCO
low. The loop BW is 80 kHz, the reference spur level is Lt -70 dBc with a 1MHz reference frequency and total loop filter capacitance of 31 pF. The measured phase noise is Lt -78 dBc/Hz and -115 dBc/Hz at 10 kHz and 1MHz offsets, respectively. This 0.23 mm
²
PLL is fabricated in a 90 nm standard digital CMOS process and consumes 10 mW from a 1.2 V supply.