A 5.8GHz low-IF multi-data rate GFSK transceiver with clock recovery and integrated 21dBm power amplifier

A highly integrated 5.8GHz transceiver capable of supporting multiple data rates has been designed in 0.18um SiGe BiCMOS for digital cordless phones and streaming audio applications. It also has a clock data recovery (CDR) circuit which can be supplied to baseband chips in conjunction with the digital received data. The transmitter with an integrated power amplifier consumes 185mA achieving an output power of 20.5dBm and the receiver consumes 65mA achieving a sensitivity of −103.5dBm and −101.5dBm at 1.536Mbps and 2.048Mbps respectively. The active area is 7.3mm
²
.