A 65nm low-power CMOS transceiver for 802.11n portable application

A low-power transceiver for 802.11n in 65 nm CMOS technology is presented. It supports 2times2 MIMO to satisfy the requirement of the draft 802.11n standard. In receiver chain it shows 5.3 dB low noise figure. In transmit chain an on-chip PA driver delivers 9 dBm output P
_1dB
. -20 to 100degC operation temperature is achieved. A SigmaDelta fractional-N synthesizer is used to support variable reference frequency when using the RF IC in different application. It consumes 35.5 mA for receiver chain and 77 mA for transmitter chain. All circuits in the presence are protected by LDO (low drop-output regulator) which isolate noise from each block and make easy-design in the future integration with digital circuits. The low power consumption, compactness and robustness make this transceiver suitable to integrate with digital base band circuits for variable portable application system.