Memory effect in MOS structures containing amorphous or crystalline silicon nanoparticles

Metal-oxide-silicon structures are fabricated by sequential physical vapor deposition of SiO
_x
(x=1.15) and RF sputtering of SiO
₂
on n-type crystalline silicon. High temperature annealing in an inert gas ambient at 700degC or 1000degC is used to grow amorphous or crystalline silicon nanoparticles in the SiO
_x
layer. The nanoparticle formation is proven by infrared transmission and Raman scattering measurements. The annealing is also used to form a dielectric layer with tunneling thickness at the silicon wafer/insulator interface. High frequency C-V measurements show that both types of structures can be charged negatively/positively by applying a positive/negative voltage on the gate. The structures with amorphous silicon nanoparticles show lower defect density at the interface between the wafer and the tunnel silicon oxide, lack of fluctuations of the C-V characteristics over the wafer and better reliability when compared to the nanocrystal ones. The most essential advantage is their better retention characteristics; upon negative charging; they retain about 60% of the negative charge trapped in the nanoparticles after 96 h while the structures with nanocrystals retain about 50% after 22 hours.