A simulation study of the bit interference effects in an ultra-thin-body, double-gate, trapped-charge-storage type non-volatile memory cell

Bit interference effects in an ultra-thin body, double-gate, trapped-charge-storage type non-volatile memory cell are investigated through two-dimensional device simulations. Though such device is more scalable and has a larger current drive, it is found that the bit states on the two sides of the “common” body would interact with each other if the body is too thin. The remote charge effect, the remote punch-through effect, and the suppressed read-through capability are clarified to be the major killing factors. If there is a higher intrinsic-V
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along the cell’s channel beyond the active thin-body regions, part of the created memory window will be shadowed. Such interferences would become the worst as these cells are arranged in an array having the common-gate feature.