Multi-bit upsets in 65nm SOI SRAMs

We study multi-bit upsets (MBU) in 65 nm SOI SRAMs. Proton beam and thorium foil experiments demonstrate that SOI SRAMs have lower soft error rate than bulk SRAMs. Monte Carlo SER simulations show that SOI SRAMs have a lower fraction of MBU than bulk SRAMs. The probability of MBU correlates with the spacing of sensitive devices in neighboring cells.