On the role of timing masking in reliable logic circuit design

Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking mechanisms: logic, timing and electrical. Most previous papers focus on logic and electrical masking. Here, we develop static and statistical analysis techniques to estimate timing masking through the error-latching window of each gate. Our SER analysis algorithms incorporating timing masking are 10 - 100x faster than comparable evaluators and can be used in synthesis and layout. We show that 62% of gates identified as error-critical using timing masking would not be identifiable by considering only logic masking. Furthermore, hardening the top 10% of error-critical gates leads to a 43% reduction in the SER. We also propose to decrease the error-latching window of each gate by relocating it such that path lengths to primary outputs are equalized. Our results show that this technique yields 14% improvement in SER with no area overhead.