Phase-adjustable Error Detection Flip-Flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling

Error detection FFs for dynamic voltage scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.