A 60GHz Low Power CMOS Demodulator for Multi-Gigabit Wireless Receiver Systems

We have developed a low power demodulator for a 60 GHz receiver using 0.13 um CMOS technology. The demodulator consists of two blocks, which are a detector and a post amplifier. The detector detects and demodulates a received signal by using a square-law-detection technique. In this case, because there is no millimeter wave oscillator for frequency conversion, the receiver block becomes simplified, miniaturized, and a structure for low power consumption. A microstrip line has been used for constructing matching networks. Also, a lambda/4 open stub is used for perfect rejection of a 60 GHz signal between the detector and the post amplifier. The post amplifier is composed of an input and output buffer and a gain stage. The cutoff frequency of the post amplifier is 2 GHz, and it has a flat gain within the bandwidth. Thus, the post amplifier acts like a low pass filter, which causes the demodulator not to need any filters and simplifies the system. The 2 Gbps demodulated amplitude-shift-keying (ASK) signal is obtained when the carrier frequency is 60 GHz. The input return loss is less than 25 dB at the center frequency of 60 GHz; the conversion gain of the demodulator is 7 dB when the input power of a demodulator is -13 dBm. The total power consumption is 21.4 mW. These results indicate that the proposed low power demodulator is suitable for 60GHz portable systems.