Novel bus termination schemes to reduce IO power consumption on low power intel small form factor platforms

In small form factor (SFF) platforms, motherboard space, and power are some of the most critical factors for their design. System memory bus is one of the major contributors to the I/O power consumption. Historically, the memory bus has always been terminated on the motherboard at the receiver end to meet SI/timing requirements. But these terminations result in significant power dissipation. This paper investigates the impact of removing these terminations [No-ODT (On Die Termination) for Data/Strobe and No-Rtt-Parallel termination for Command/Control (CMD/CNTL) for different memory configurations], and provides motherboard routing recommendations to support No-ODT/No-Rtt without violating SI/timing specs. This paper also highlights the savings in power and motherboard space achieved by removing these terminations.