A VLSI Architecture Suitable for Mid-Level Image Processing

Despite the constant research in this field in the last 40 years, computer vision still remains as a very challenging task. Computer vision techniques used to be categorized into levels, according to the amount of cognition embodied and the output provided. Taking into account the 3-levels approach, the goal of this work is the development of a VLSI architecture suitable for mid-level processing tasks. A software evaluation has been followed by its hardware equivalent implementation. The resulting architecture takes 11,165 logic elements and proved to be around 2.5 times faster than its software counterpart.