A Design Method for Ultra-High Speed for A New Wave Pipeline-based Circuit

This paper presents a new wave pipeline design method for combinational circuits with focus on circuit speed optimization. Today's high speed circuit and advanced fabrication technology dictates delay uncertainty an extremely important issue in circuit design. The proposed method seek a speed optimization opportunity by temporally superimposing the datawaves in the circuit without creating any spatial collision between adjacent datawaves, while conventional wave pipeline designs do not allow any temporal superimposition between adjacent datawaves, which may result in a serious speed loss of the circuit. By this intrinsic advantage of the proposed method over conventional wave pipeline, the proposed new wave pipeline can achieve a better clock cycle time (CCT) than conventional wave pipeline. The proposed new method is simulated and validated against ISCAS benchmark circuits. The results show that the new method can achieve over a 48% performance enhancement on clock cycle time compared with the conventional wave pipeline.