A New Calibration Method for Sampling Clock Skew in Time-interleaved ADC

A sampling clock skew calibration method with a new calibration signal addition circuit is presented in this paper. The clock skew is detected using a calibration signal, and the calibration is done by adjustment of sample clock delay. The new calibration signal addition circuit consisting of small capacitors and a few switches has little interference to the input signal, and makes it possible for the proposed calibration method to operate at background.