An efficient power reduction technique for flash ADC

An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. As an example of 6-bit flash ADC, we use three extra comparators in our design to divide the next stage into four sections and control timing signal whether can proceed to the 63 original comparators or not. With a timing period, only two sections of the comparators are allowed to operate, which achieve the aim of the low power consumption. Experimental results show that this new method consumes about 17.05mW at 200 MHz with 3.3V supply voltage in TSMC 0.35μm 2P4M process. Compared with the traditional flash ADC, our low power method can reduce up to 76.4% in power consumption. The DNL of our proposed flash ADC is within 0.2LSB/−0.5LSB, and the INL is within 0.7LSB/−0.3LSB. The chip area occupies 0.8×1.4mm
²
with I/O pads.