A Passive Filter Aided Timing Recovery Scheme

This paper presents a passive filter for the front end of a high speed serial link receiver to aid timing recovery. The filter provides simultaneous lowpass and highpass transfer characteristics to generate the data and its slope respectively. Slope detection is demonstrated at 10-Gb/s. As a proof of concept, the filter was used to extract a 2-GHz clock from a 2-Gb/s 2
³¹
–1 random data sequence based on a modified minimum mean squared error (MMSE) criterion. The circuit is fabricated in a 0.18 μm CMOS process and consumes 21.6 mW from a 1.8V supply.