On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits

Power-gating has proved to be one of the most effective solutions for reducing stand-by leakage power in nanometer-scale CMOS circuits, and different strategies and algorithms for its application have been proposed recently. Unfortunately, power-gating comes with its own set of costs: Performance degradation, area increase, dynamic power increase and routing congestion. When a decision to power-gate a design has to be taken, pros and cons of power-gating have to be properly weighted to achieve optimal results. In this paper, we define “Figures of Merit” (FoMs) for power-gating, which can be used by designers to better understand the benefits and costs of power-gating, thereby allowing them to achieve optimal results. We then quantify the FoMs by applying a state-of-the-art, industry-strength powergating flow on a set of designs implemented onto an industrial 65nm CMOS process, and provide insightful discussion on how optimum power-gating can be achieved.