Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits

Data stability of Static Random Access Memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also important sources of leakage since the majority of transistors are utilized for on-chip memory in today’s high performance microprocessors and systems-on-chips. The use of work-function engineering to control the threshold voltage of FinFETs is explored in this paper for achieving minimum sized multi-threshold-voltage (multi-V
t
) six transistor (6T) SRAM cells with sufficient data stability and lower leakage power consumption characteristics. A work-function optimization methodology for designing low power and high speed memory circuits is presented. With the proposed multi-V
t
design methodology based on gate work-function engineering, the leakage power is reduced by up to 65X as compared to a standard single low threshold voltage (single-low-V
t
) SRAM circuit sized for similar data stability in a 32nm FinFET technology.