Pseudorandom Clock Signal Generation for Data Conversion in a Multistandard Receiver

In previous work, a non-uniform sampling (NUS) technique to control analog-to-digital conversion (ADC) in a multistandard radio receiver was proposed. In this context of wide band radio signals, the NUS-based ADC offers the advantages of relaxing antialiasing filter (AAF) constraints, decreasing the sampling frequency average and reducing ADC dynamic power consumption. In this paper, we focus on generating non-uniform clock for the sample and hold block of the ADC. The proposed non-uniform clock is based on quantified clock timing. Non-uniform clock is generated from digital control unit (DCU). The DCU is composed of a Gray counter, a linear feedback shift register (LFSR) and a multiplexer to generate specified signals and to select the required clock phase. Simulation results show that performances are similar for conventional uniform sampling (US), additive random sampling (ARS) and time quantized additive random sampling (TQ-RS) for different quantizing factors.